A minimal, event-driven consistency kernel for many-core processors which provides the necessary low level operations for software controlled consistency protocols that can be used by higher layers.

• Duration: 2013 to 2016
• Funding: DFG-Project

Computational power of single-core processors currently reaches a technological saturation point. Further increases are only achievable through the employment of multiple cores. While current microprocessor architectures employ up to 16 cores, some systems offer up to 100 cores on a single chip. Future development is expected to yield architectures with up to 1000 cores. For improved scalability, these processors employ extremely powerful communication networks (network on chip, NOC). They de facto combine the features of a distributed system and NUMA architectures. The ultra low latency and high bandwidth of these networks enable the possibility to shift replication and consistency maintenance away from hardware to the operating system and runtime libraries. This way problems like false sharing, cache trashing and memory bandwidth bottlenecks can be handled more flexible.

The goal of the CoKe project is the design of a minimal, event-driven consisteny kernel for many-core processors. This kernel will provide the necessary low level operations for software controlled consistency protocols that can be used by higher layers. The kernel is the basis for the design of custom "consistency machines" that implement different relaxed memory semantics for software- and page-based shared memory.

These contents are currently under construction. A complete list of all publications can be found in the publication area.