Informatik-Kolloquium

Im Rahmen des Informatik-Kolloquiums möchten wir Sie recht herzlich zum Institus-Talk

Fostering the use of machine learning on board to satellite: the CloudScout case study and beyond

einladen

Agenda:

Luca Fanucci, Space Activities overview at Pisa University and Ingeniars spin-off company
Gianluca Giuffrida, CNN-based on-the-edge clouds detector: the CloudScout case study
Gianmarco Dinelli, FPGA implementation of CloudScout CNN: advantages and disadvantages
Pietro Nannipieri, The ICU4SAT project idea: a Pisa and Brandenburg Universities collaboration
All,  brainstorming

am:                        Mittwoch, 09.12.2020

um:                        15:00 - 16:30 Uhr

Webex-Daten:  https://b-tu.webex.com/b-tu-en/j.php?MTID=m8ffc4f6809b871ead49a31fb9e2a6cd6
                         Meeting number: 121 053 7857  Password: 99sTN33kcRM

Abstract

Fostering the use of machine learning on board to satellite: the CloudScout case study and beyond
Machine Learning (ML) has already demonstrated its capability to solve complex problem in the cloud. With the advancement of dedicated embedded hardware accelerators, the potential of ML can be exploited also at the edge. This opens very interesting scenarios also for space applications, both for communication/control and payload levels. In fact, at control level ML algorithms can be exploited to control the navigation of satellites, using images of target planets or moon craters as reference points. At payload level, instead, ML can be used to simplify Earth Observation for remote sensing applications, directly elaborating data on-board reducing the dependency with the earth: such as cloud detection, fire detection, object detection, land cover / land use classification, etc. For these image-based scenarios Convolutional Neural Networks (CNNs) and theirs derivates represent one of the most promising algorithms.
This seminar will present some research activities on CNN-based algorithms for embedded and low power platforms at the edge recently developed at the University of Pisa. Starting from the CloudScout CNN recently launched on board of the Phisat-1 mission we will discuss several trade-off in terms of output accuracy, power consumption and memory requirements for commercial (e.g. Intel Movidius Myriad-2) and dedicate hardware accelerators based on FPGA. Finally we will present the concept of the Instrumentation Control Unit for Satellite Application (ICU4SAT) project to be developed in collaboration with Brandenburg University of Technology – Cottbus-Senftenberg.

Speakers Short Bio

Luca Fanucci (Fellow, IEEE) received the Laurea and Ph.D. degrees in electronic engineering from the University of Pisa in 1992 and 1996, respectively. From 1992 to 1996, he was a Research Fellow with the European Space Agency (ESTEC), Noordwijk, The Netherlands. From 1996 to 2004, he was a Senior Researcher with the Italian National Research Council, Pisa. He is currently a Professor of microelectronics with the University of Pisa. His research interests include several aspects of design technologies for integrated circuits and electronic systems, with particular emphasis on system-level design, hardware/software co-design and sensor conditioning, and data fusion, and also wireless communications, low-power multimedia, automotive, healthcare, ambient assisted living, and technical aids for independent living. He is the coauthor of more than 400 journal articles and conference papers and a co-inventor of more than 40 patents. He is a member of the Editorial Board of Technology and Disability (IOS Press) Journal. He has served in several technical programme committees of international conferences. He was the Program Chair of DSD 2008 and DATE 2014 and the General Chair of DATE 2016 and HiPEAC 2020.

Gianluca Giuffrida got the bachelor’s degree in computer engineering at the Università degli studi di Catania in 2015. He got the master’s degree in Embedded Computing System at the University of Pisa in 2018. Master’s thesis work was based on an autonomous robotic arm for people with disabilities exploiting machine learning algorithms for object detection. He is currently pursuing the PhD in Information Engineering at the University of Pisa where main research topics are Machine Learning, Artificial Intelligence, Computer Vision and Robotics. Gianluca led the development team of the CloudScout convolutional neural network which was launched on 3 September 2020 on board to the Phisat-1 mission.

Gianmarco Dinelli received the M.Sc. degree (110 cum laude) in electronic engineering from the University of Pisa, where he is currently pursuing the Ph.D. degree with the VLSI Lab, Department of Information Engineering. His work is mainly related to digital system design, from system specifications to hardware implementation on an FPGA device. His research interests include satellite on-board data-handling subsystem and on the design of FPGA-based hardware accelerators for machine learning algorithms (e.g. CNNs), with particular attention to low power and resource-constrained on-the-edge applications.

Pietro Nannipieri got his Ph.D. in Information Engineering from University of Pisa in 2020 cum laude. His interests are digital and VLSI design as well as electronics for space applications. Pietro spent several Months in 2019 as Visiting Researcher in the TEC-EDP Section in ESTEC (ESA), where he carried out different qualification test on the SpaceFibre technology. He is currently a Post-doc researcher in the VLSI lab of the information engineering department, University of Pisa. His work mainly focuses on the development of IPs for satellite on-board data handling, (i.e. SpaceFibre), but also on signal processing and hardware cryptography.

Informatik-Kolloquium

Im Rahmen des Informatik-Kolloquiums möchten wir Sie recht herzlich einladen zum Vortrag von Frau Dr. Alexandra Kourfali (Universität Ghent, Belgien)

 

zum Thema:      Novel Hardware Verification Methods for FPGAs”

 

am:                        Montag, 02.03.2020

um:                        11:00 Uhr

im:                          Verfügungsgebäude 1C, Raum 1.24

Abstract:
Due to the continuously shrinking transistor sizes, anomalies are caused in the design that needs contingency plans. These contingency plans need to be available as soon as possible in the design of an IC, to avoid costly redesigns and other associated delays. Additionally, as the number of transistors inside ICs increases, thus allowing more complex digital designs to be realized, debugging and verifying these designs has become an increasingly difficult task. Moreover, multiple designs contain a safety-critical feature. They are in need to comply with specific safety-critical standards, making IC reliability a fundamental concern in the design and manufacturing process. Various hardware verification techniques exist, that can be used based on the requirements of each design and at different stages in the design flow. There is a trade-off between speed, design complexity, internal signal observability, and required fault coverage.

This talk will address these issues, and discuss the creation of verification methods that cover bugs, permanent faults, and soft errors. With interest in commercial SRAM-based FPGAs, this talk addresses the problems of providing continuous operation after an error occurred by achieving a runtime reconfigurable recovery from a failure, and to ensure that bugs that have escaped pre-silicon validation are detected. In particular, emulation-based verification techniques that are dependent on a long verification cycle and need significant resources are addressed throughout the talk, namely fault injection, fault tolerance, and in-circuit debugging.
The objectives for this work are focused on providing novel methods, tools, and design techniques for hardware verification that can be either applied for FPGA prototyping during ASIC verification or when an FPGA is the final product. They address major industry bottlenecks, namely area and time overhead, limited internal observability, long recompilation/reconfiguration times, and intolerance to soft errors and other radiation effects.


Zum Kolloquium am Montag, dem 13.01.2020, laden wir alle Interessenten recht herzlich ein.

Prof. Paolo Rech, Universidade Federal do Rio Grande do Sul (Brasilien)
spricht zum Thema:
Reliability of Computing Systems in the Era of Autonomous Vehicles and Supercomputers

Termin: 10:00 Uhr
Raum:    Verfügungsgebäude 1C, Seminarraum 0.01

Abstract:
Reliability is one of the major concerns for both safety-critical and High-Performance Computing applications. A neutron impact can generate faults in computing devices, leading to application crashes, wrong results, and system hangs. Several evidence showed that neutron-induced faults have corrupted large-server operations, have caused unexpected behaviours in airplanes, lead to car accidents, and even influenced politics results. In the talk we will briefly cover the effects of neutron impact on computing systems and applications. Particular emphasis will be given to self-driven cars, which is the newest trend in the automotive industry. We will present the results of several experiments on object-detection frameworks for automotive applications and show that neutrons can effectively change the way a vehicle senses objects, potentially leading to accidents. Lately, novel architectural solutions, such as heterogeneous computing and mixed-precision architectures, have been introduced to increase devices computational efficiency. We will discuss if and how we can take advantage of these novel architectural solutions to improve applications' reliability without unnecessary overhead. Particular attention will be given to the reliability of Xilinx Field-Programmable Gate-Arrays (FPGA), Intel Xeon Phis, NVIDIA Graphics Processing Units (GPUs), ARM embedded devices, and AMD heterogeneous devices.


Zum Kolloquium am Montag, dem 09.12.2019, laden wir alle Interessenten recht herzlich ein.

Prof. José Rodrigo Azambuja, Universidade Federal do Rio Grande do Sul (Brasilien)
spricht zum Thema:
Fault Tolerance Techniques for Graphics Processing Units

Termin: 15:30 Uhr
Raum:    Verfügungsgebäude 1C, Seminarraum 0.01

Abstract:
Graphics Processing Units (GPUs) have evolved from devices specially designed for graphics rendering to general-purpose accelerators for High-Performance Computing (HPC) applications and, more recently, to expedite the training and execution of Deep Learning frameworks. Artificial Neural Networks (ANNs) are becoming a widely adopted computational approach in many fields, such as data mining, pattern recognition, robotics, data analytics. Lately, ANNs have been extensively used to detect objects in a scene in realtime, an essential function in modern  autonomous vehicles. As GPUs moved in HPC and safety-critical domains, questions about their  reliability started to raise. This talk discusses the use of selective fault tolerance techniques and approximate computing to harden such devices.


Zum Kolloquium am Montag, dem 2. Dezember 2019, laden wir alle Interessenten recht herzlich ein.

 Prof. Dr. Martin Ziegler (KAIST School of Computing, Daejeon, South Korea)

spricht zum Thema:

Computer Science for Numerics

Beginn:  13:45 Uhr
Ort:   Lehrgebäude 1 A, Raum 304

Abstract:
Since introduction of the IEEE 754 floating point standard in 1985, numerical methods have become ubiquitous - and increasingly sophisticated.
With growing code complexity of numerical libraries grows the need for rigorous Software Engineering methodology: as provided by Computer Science and
state of the art regarding digital processing of discrete data, but lacking in the continuous realm.
We apply, adapt, and extend the classical concepts - specification, algorithmics, analysis, complexity, verification - from discrete bit strings, integers, graphs etc.
to real numbers, converging sequences, smooth/integrable functions, bounded operators, and compact subsets.
A new paradigm bridged between the BSS model and Computable Analysis.
It formalizes mathematical structures as continuous abstract data types with rigorous computable semantics.

Following the last decades' seminal interplay between Discrete Mathematics and Computer Science,
Future Numerics revolves around Computer Science bridging between Pure and Applied continuous Mathematics.

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Zum Kolloquium am Montag, dem 25.11.2019, laden wir alle Interessenten recht herzlich ein.

 Prof. Antonio Beck, Universidade Federal do Rio Grande do Sul (Brasilien)
spricht zum Thema:
Adaptability – The Key for Future (Embedded?) SystemsAbstract

Termin: 15:30 Uhr
Raum:   Lehrgebäude 1A, Raum 304

Abstract:
Most traditional hardware architectures are based on a fixed design that limits its run-time adaptability. Therefore, these platforms are unable to cope with the varying application behavior when one considers non-functional requirements that are increasing in importance, such as fault tolerance, power, energy, or even quality. In this context, this talk will discuss several approaches to adapting the hardware dynamically to the application at hand and deliver the best trade-off among these non-functional requirements, according to a given set of design choices


Vom 09.09.-13.09.2019 findet in Cottbus die Tagung Declare 2019 zur Deklarativen Programmierung bestehend aus folgenden Events statt:

  WLP 2019 - 33rd Workshop on
     (Constraint) Logic Programming,
  WFLP 2019 - 27th International Workshop on
     Functional and Logic Programming  und
  INAP 2019  - 22nd International Conference on Applications of
     Declarative Programming and Knowledge Management


Informatik-Kolloquium

Zum Kolloquium am Donnerstag, dem 13.06.2019, laden wir alle Interessenten recht herzlich ein.

 Prof. Fabian Vargas, Catholic University – PUCRS, Porto Alegre, Brasilien spricht zum Thema:
„Recent research topics in the Signals & Systems for Computing (SiSC) Group“

Termin: 14:30 Uhr
Raum: Verfügungsgebäude, Seminarraum 0.01

Abstract:
The presentation is split in two parts. First, we address research on the development of a combined ionizing radiation & electromagnetic interference test procedure to achieve reliable integrated circuits. Then, in the second part, we focus research on the development of  a new approach to support mixed-criticality workload execution and a fault-free task scheduling algorithm in a multicore processor-based embedded system.

Part I: International standards have been proposed and used to test Integrated Circuits (ICs) for Total-Ionizing Dose (TID) and Single-Event Upset (SEU) as well as for Electromagnetic Interference (EMI). Nevertheless, these standards are separately applied to the IC or electronic system, one after the other, and do not take into account the combined effects of these types of radiation may take over the ICs. In more detail, there is no standard that rules combined tests for TID, SEU and EMI. This topic addresses this lack of product quality information and develop a new methodology to improve the reliability of ICs by performing combined tests for TID, SEU and EMI. We also present recent experimental results from combined measurements we performed on a commercial FPGA IC widely used in critical embedded applications such as aerospace and automotive.
Such results strongly suggest that the effects of radiation are not negligible and should be taken into account if one intends to design reliable embedded systems.

Part II: Recently, the use of multicore processors in general-purpose real-time embedded systems has experienced a huge increase. Unfortunately, critical applications are not benefiting from this type of processors as one could expect. The major obstacle is that we may not predict and provide any guarantee on real-time properties of software running on such platforms. The shared memory bus is among the most critical resources,
which severely degrades the timing predictability of multicore software due to the bus access contention between cores. This part of the talk presents the current research state on a new approach to support mixed-criticality workload execution in a multicore processor-based embedded system. The approach is based on the use of an infrastructure intellectual property (I-IP) core named Deadline Enforcement Checker (DEC), implemented in hardware, which automatically manages the execution of any number of cores in a TDMA-based bus access police while guaranteeing critical task schedulability. This approach allows the exploitation of the maximum performance offered by a multiprocessing system while guaranteeing critical task schedulability, i.e., that the critical task execution will not violate timing deadline. A case-study based on a quad-core version of the LEON3 softcore processor was implemented in VHDL language. Practical experiments demonstrate the proposed technique is very effective on combining system high performance with critical task schedulability within timing deadline. We also present a second functionality of the DEC I-IP, which aims at monitoring the scheduling process in an Operating System (OS). A preliminary case-study is under implementation, where the OS is running the Early Deadline First (EDF) task scheduling algorithm. The goal of the DEC I-IP, in this case, is to detect faults that escape detection by the native fault detection mechanisms embedded in the OS kernel.

Announcement


Informatik-Kolloquium

Zum Kolloquium am Dienstag, dem 28.05.2019 laden wir alle Interessenten recht herzlich ein.

Dipl.-Inf. Thomas Prescher und Dipl.-Inf. Julian Stecklina von der Cyberus Technology GmbH aus Dresden sprechen zum Thema:
"LazyFP: Discovering Side-Channels is not a Beach Vacation"

Termin: Dienstag, 28.05.2019  15:30 Uhr
Raum: ZHG, Hörsaal C

Abstract:

In 2018, we jointly discovered and responsibly disclosed the LazyFP microarchitectural side-channel vulnerability (CVE-2018-3665). LazyFP is a Meltdown-type attack on hypervisors and operating systems that use lazy FPU context switching and allows recovery of FPU/SSE/AVX register sets across process and virtual machine boundaries. The underlying microarchitectural flaw is present in all modern Intel Core-based processors.

In this talk, we look at this vulnerability in two ways. On the technical side, we review the different register sets on an x86 CPU and how operating system kernels and hypervisors manage them. We describe how the obscure Lazy FPU context switching optimization together with a microarchitectural weakness form an information disclosure vulnerability. We explain why FPU registers can even contain interesting secrets and how this vulnerability was mitigated.

On the non-technical side, we tell the story of two systems developers working for different companies, one at a small German cyber-security company and one at an American trillion-dollar corporation, finding a security issue in Intel's main product. Looking back on these turbulent events, we detail our personal lessons learned and how we would approach an event like this in the future.

Einladung mit Abstract


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