akademischer Mitarbeiter

M. Sc. Johannes Knödtel
Verfügungsgebäude 1C, Raum 1.39

T: +49 (0) 355 69 2591
F: +49 (0) 355 69 2027
johannes.knoedtel(at)b-tu.de

Veröffentlichungen

2023

  • Knödtel J., Reichenbach M.:
    Datapath Optimization for Embedded Signal Processing Architectures utilizing Design Space Exploration
    In: Proceedings of the 2023 Workshop on System Engineering for constrained embedded systems (RAPIDO 2023), January 17–18, 2023, Toulouse
    DOI: https://doi.org/10.1145/3579170.3579257
  • Knödtel, J., Rachuj, S., Reichenbach, M.:
    Suitability of ISAs for Data Paths Based on Redundant Number Systems: Is RISC-V the best?
    In: 2022 25th Euromicro Conference on Digital System Design (DSD)
    DOI: https://doi.org/10.1109/DSD57027.2022.00041

2022

  • Scheibe C., Kuri A., Feng Y., Zhao L., Xiong X., La Seta P., Peng Liang X., Knödtel J., Holzinger P., Reichenbach M., Mehlmann G.:
    Interfacing real-time and offline power system simulation tools using UDP or FPGA systems
    In: Electric Power Systems Research, Volume 212
    ISSN: 0378-7796
    DOI: https://doi.org/10.1016/j.epsr.2022.108490

2021

  • Fritscher M., Knödtel J., Mallah M., Pechmann S., Quesada EP., Rizzi T., Wenger C., Reichenbach M.:
    Mitigating the Effects of RRAM Process Variation on the Accuracy of Artifical Neural Networks
    21th International Conference, SAMOS 2021
  • Fritscher M., Knödtel J., Reiser D., Mallah M., Pechmann S., Fey D., Reichenbach M.:
    Simulating large neural networks embedding MLC RRAM as weight storage considering device variations
    In: Proc. of 12th IEEE Latin America Symposium on Circuits and System 2021
  • Reichenbach M., Knödtel J., Rachuj S., Fey D.:
    RISC-V3: A RISC-V Compatible CPU with a Data Path Based on Redundant Number Systems
    In: IEEE Access (2021), S. 1-1
    ISSN: 2169-3536
    DOI: 10.1109/ACCESS.2021.3063238

2020

  • Knödtel J., Fritscher M., Reiser D., Fey D., Breiling M., Reichenbach M.:
    A Model-to-Circuit Compiler for Evaluation of DNN Accelerators based on Systolic Arrays and Multibit Emerging Memories
    9th International Conference on Modern Circuits and Systems Technologies, MOCAST 2020 (Bremen, 7. September 2020 - 9. September 2020)
    In: 9th International Conference on Modern Circuits and Systems Technologies, {MOCAST} 2020, Bremen, Germany, September 7-9, 2020 2020
    DOI: 10.1109/MOCAST49295.2020.9200241

2019

  • Fritscher M., Knödtel J., Reichenbach M., Fey D.:
    Simulating memristive systems in mixed-signal mode using commercial design tools
    26th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2019 (Genoa, 27. November 2019 - 29. November 2019)
    In: 2019 26th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2019 2019
    DOI: 10.1109/ICECS46596.2019.8964856
  • Peschel J., Knödtel J., Pérez E., Reichenbach M., Wenger C., Fey D.:
    Optimizing Multi-State Reliability in ReRAM Arrays using an Automated Device Selection Method
    MEMRISYS 2019 International Conference on Memristive Materials, Devices & Systems (International Congress Center Dresden, 8. Juli 2019 - 11. Juli 2019)

2018

  • Knödtel J., Schwabe W., Lieske T., Reichenbach M., Fey D.:
    A Novel Methodology for Evaluating the Energy Consumption of IP Blocks in System-Level Designs
    28th International Symposium on Power and Timing Modeling, Optimization and Simulation (Platja D’Aro, 2. Juli 2018 - 4. Juli 2018)
    In: 2018 28th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS) 2018
    DOI: 10.1109/PATMOS.2018.8464149
  • Wust D., Fey D., Knödtel J.:
    A programmable ternary CPU using hybrid CMOS/memristor circuits
    In: International Journal of Parallel, Emergent and Distributed Systems (2018), S. 1--21
    ISSN: 1744-5760
    DOI: 10.1080/17445760.2017.1422251

2017

  • Wust D., Biglari M., Knödtel J., Reichenbach M., Söll C., Fey D.:
    Prototyping Memristors in Digital Systems with an FPGA-Based Testing Environment
    International Symposium on Power and Timing Modeling, Optimization and Simulation (Thessaloniki, 25. September 2017 - 27. September 2017)
    In: Power and Timing Modeling, Optimization and Simulation (PATMOS), 2017 27th International Symposium on 2017
    DOI: 10.1109/PATMOS.2017.8106978
    URL: http://ieeexplore.ieee.org/document/8106978/