Development of smaller and more energy-efficient AI chips

The aim of the new DFG project entitled "Computational Coding" is to research a new approach for the energy-efficient realization of artificial intelligence algorithms in hardware.

In particular, neural networks are the focus of scientists at BTU Cottbus-Senftenberg and Friedrich-Alexander-Universität Erlangen-Nürnberg (FAU). The energy-efficient chips developed in the project are the basis for numerous applications such as image and speech processing.

For the inference of neural networks, i.e. the "training" of applications in AI, so-called weight matrices are successively multiplied by corresponding vectors. In this way, the "brain" of artificial intelligence evolves. These operations involve an extremely high computational effort, and they are a challenge for currently available processors. Against this background, the simplification of these weight matrices by a new mathematical method called matrix decomposition is the focus of the joint project.

For this purpose, the scientists decompose the original weight matrices into partial matrices with a special structure. This special structure can then be used to create a new type of processor. These are specifically optimized for this type of decomposition. This process makes it possible to generate new AI processors that are six times smaller. Accordingly, energy consumption can also be minimized. The chips developed in this way can then serve as the basis for many applications, such as signal analysis in wearable sensors.

For their research, the scientists from both universities, led by Dr.-Ing. Marc Reichenbach from the Chair of Computer Engineering at BTU and Prof. Dr.-Ing. Ralf Müller from the Chair of Digital Transmission at FAU, are combining their expertise in the fields of information theory and computer architecture.

Contact

Dr.-Ing. Marc Reichenbach
T +49 (0) 355 69-2026
marc.reichenbach(at)b-tu.de
HBM Board (Photo:FAU)