2024

• Fritscher M, Wenger C, Krstic M:
  From Device to Application - Integrating RRAM Accelerator Blocks into Large AI Systems
  IEEE Computer Society Annual Symposium on VLSI, 2024
• Fritscher M, Uhlmann M, Ostrovskyy P, Reiser D, Chen J, Schulze C, Schubert A, Kahmen G, Fey D, Reichenbach M, Wenger C, Krstic M:
  Area-efficient Digital Design using RRAM-CMOS Standardcells
  IEEE Computer Society Annual Symposium on VLSI, 2024
• Kliemt J, Fritscher M, Fey D:
  Comparison of a Binary Signed-Digit Adder with Conventional Binary Adder Circuits on Layout Level
  37th International Conference on Architecture of Computing Systems (ARCS), 2024
• Wen J., Vargas F., Zhu F, Reiser D, Baroni A, Fritscher M, Perez E, Reichenbach M, Wenger C, Krstic M:
  Cycle-Accurate FPGA Emulation of RRAM Crossbar Array: Efficient Device and Variability Modeling with Energy Consumption Assessment
  25th IEEE Latin American Test Symposium, 2024

2023

• Reiser D, Reichenbach M, Rizzi T, Baroni A, Fritscher M, Wenger C, Zambelli C, D. Bertozzi D:
  Technology-Aware Drift Resilience Analysis of RRAM Crossbar Array Configurations
  21st IEEE Interregional NEWCAS Conference, 2023
• Uhlmann M., Perez-Bosch Quesada E, Fritscher M, Perez E, Schubert M.A., Reichenbach M, Ostrovskyy P, Wenger C, Kahmen G:
  One-Transistor-Multiple-RRAM Cells for Energy-Efficient In-Memory Computing
  21st IEEE Interregional NEWCAS Conference, 2023
• Fritscher M, Veronesi A , Baroni A, Wen J, Spätling T, Mahadevaiah M. K., Herfurth N., Perez E., Ulbricht M , Reichenbach M, Hagelauer A, Krstic M .:
  Prototyping reconfigurable RRAM-based AI accelerators using the RISC-V ecosystem and Digital Twins
  ISC High Performance 2023 International Workshops. ISC High Performance 2023

2022

• Fritscher M, Dengler G, Bleibaum C, Niebisch M, German R.:
  Accelerating Veins Simulations by Utilizing Task Parallelism on a HPC Cluster Without Introducing Major Inaccuracies
  13th IEEE/IET International Symposium on Communication Systems, Networks and Digital Signal Processing

2021

• Fritscher M., Knödtel J., Mallah M., Pechmann S., Quesada EP., Rizzi T., Wenger C., Reichenbach M.:
  Mitigating the Effects of RRAM Process Variation on the Accuracy of Artifical Neural Networks
  21th International Conference, SAMOS 2021
• Fritscher M., Knödtel J., Reiser D., Mallah M., Pechmann S., Fey D., Reichenbach M.:
  Simulating large neural networks embedding MLC RRAM as weight storage considering device variations
  In: Proc. of 12th IEEE Latin America Symposium on Circuits and System 2021

2020

• Knödtel J., Fritscher M., Reiser D., Fey D., Breiling M., Reichenbach M.:
  A Model-to-Circuit Compiler for Evaluation of DNN Accelerators based on Systolic Arrays and Multibit Emerging Memories
  9th International Conference on Modern Circuits and Systems Technologies, MOCAST 2020 (Bremen, 7. September 2020 - 9. September 2020)
  In: 9th International Conference on Modern Circuits and Systems Technologies, {MOCAST} 2020, Bremen, Germany, September 7-9, 2020 2020
  DOI: 10.1109/MOCAST49295.2020.9200241

2019

• Fritscher M., Knödtel J., Reichenbach M., Fey D.:
  Simulating memristive systems in mixed-signal mode using commercial design tools
  26th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2019 (Genoa, 27. November 2019 - 29. November 2019)
  In: 2019 26th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2019 2019
  DOI: 10.1109/ICECS46596.2019.8964856