The stack segment contains local data as well as saved register values. These register values are vulnerable when local data overflows past its defined boundaries. For the ESP32 register saving is handled in an exception context. The task for the student is to implement a separation of the normal stack data and saved register values to increase the systems safety and security.

Supervisor: Kai Lehniger M.Sc. (lehniger@ihp-microelectronics.com)

Various security features rely on the assumption that there is a way to store meta data that an attacker cannot access. This requires different measures to make this data unaccusable during normal operation, but accessible when needed in an efficient way. Goal of this thesis is to implement a small instruction set extension that contains dedicated instructions that use a different address translation to support memory isolation on a RISC-V system.

Supervisor: Kai Lehniger M.Sc. (lehniger@ihp-microelectronics.com)

The elliptic curve point multiplication with a scalar kP is the basic operation in cryptographic protocols for ECC. Binary kP double-and-add algorithms are vulnerable to horizontal side-channel analysis (SCA) attacks. Atomicity and regularity principles are well-known countermeasures against simple SCA attacks assuming that the different register operations cannot be distinguished by their addressing. Modern measurement equipment allows capturing traces with a high sampling rate.  Thus, the register addressing has to be evaluated as the SCA leakage source.
Nowadays, many open-source cryptographic libraries are available for the implementation of cryptographic protocols.
Some of them provide an implementation of the kP operation only. Others provide also mathematical operations in finite fields. Some libraries are claimed to be resistant to one-trace attacks, due to their constant time functions or the kP algorithms implemented corresponding to the regularity or atomicity principles.
The evaluation of the resistance against simple SCA attacks of a selected atomic pattern (or a regular) kP algorithm is the main task of this work. The selected kP algorithm has to be implemented using a selected open-source cryptographic library for an embedded device. The power and/or electromagnetic kP execution traces have to be measured and analyzed.

Possible kP algorithms, for the implementation:

1. B. Chevallier-Mames, M. Ciet, and M. Joye, “Low-cost solutions for preventing simple side-channel analysis: side-channel atomicity,” IEEE Transactions on Computers, vol. 53, no. 6, pp. 760–768, Jun. 2004, doi: 10.1109/TC.2004.13
2. P. Longa, “Accelerating the Scalar Multiplication on Elliptic Curve Cryptosystems over Prime Fields,” Cryptology ePrint Archive, 2008, Accessed: Jul. 13, 2022. [Online]. Available: eprint.iacr.org/2008/100
3. C. Giraud and V. Verneuil, “Atomicity Improvement for Elliptic Curve Scalar Multiplication,” in Proceedings of the 9th IFIP WG 8.8/11.2 International Conference on Smart Card Research and Advanced Application, Berlin, Heidelberg, 2010, pp. 80–101. doi: 10.1007/978-3-642-12510-2_7
4. D. Hankerson, J. Lopez, and A. Menezes, “Software Implementation of Elliptic Curve Cryptography over Binary Fields,” in Cryptographic Hardware and Embedded Systems — CHES 2000, Aug. 2000, pp. 1–24. doi: 10.1007/3-540-44499-8_1
5. K. Itoh, T. Izu, and M. Takenaka, “A Practical Countermeasure against Address-Bit Differential Power Analysis,” in Cryptographic Hardware and Embedded Systems - CHES 2003, Sep. 2003, pp. 382–396. doi: 10.1007/978-3-540-45238-6_30
6. M. Izumi, J. Ikegami, K. Sakiyama, and K. Ohta, “Improved countermeasure against Address-bit DPA for ECC scalar multiplication,” in 2010 Design, Automation Test in Europe Conference Exhibition (DATE 2010), Mar. 2010, pp. 981–984. doi: 10.1109/DATE.2010.5456907

Supervisor: Hon. Prof. Dr.-Ing. Zoya Dyka (dyka@ihp-microelectronics.com)

Side-channel analysis (SCA) and fault injection (FI) attacks are dangerous kinds of physical attacks against cryptographic implementations.

Most often attacked blocks are the registers: their energy consumption for data storing is successfully exploited in vertical SCA attacks and their addressing in horizontal SCA attacks. The values stored in the registers can be manipulated via FI attacks.

Randomized use of redundant hardware blocks can hide at least partially side-channel leakage. At the same time, use of the redundancy can countermeasure fault injection attacks.

Randomized re-arrangement of duplicated and/or triplicated registers during a single cryptographic operation can be a promising approach to reduce the vulnerability of cryptographic implementations to the SCA and FI simultaneously. The implementation of a such flexible redundancy support is especially difficult for cryptographic operations designed as a hardware. The flexible redundancy for registers requires a dynamically (i.e. run-time, or on-the-fly) reconfigurable voter. For ASIC designs only a kind of a pseudo-reconfigurability is possible, i.e. a voter for all reasonable combinations of duplicated and triplicated registers can be used via control signals to support such functionality.

The goals of this investigation are:

• to estimate the area (gate complexity) of the voter supporting all possible combinations of duplicated and triplicated registers for a design with n main and N redundant l-bit long registers on example of small values n, N, and l;
• to estimate the reduction of the area (gate complexity) reducing N as the basis for criterion for determining the reasonable number N of redundant registers for n main registers:
  • the vision is that for the given number n main registers and the given area overhead of X% (from the register’s area) the number of acceptable redundant registers N can be determined.

The estimations have to be performed based on the practical implementation of the voters in VHDL.

An overview of the literature is an important part of the master's thesis.

The following paper can be recommended as an introduction to the topic:

• N. Mentens, "Hiding side-channel leakage through hardware randomization: A comprehensive overview," 2017 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS), Pythagorion, Greece, 2017, pp. 269-272, doi: 10.1109/SAMOS.2017.8344639, https://ieeexplore.ieee.org/document/8344639 (https://www.esat.kuleuven.be/cosic/publications/article-2824.pdf)

Supervisor: Hon. Prof. Dr.-Ing. Zoya Dyka (dyka@ihp-microelectronics.com)

As a potential thesis topic, it is feasible to develop a demonstrator for a specific security topic. A demonstrator serves the purpose of illustrating a topic to an audience. The candidate should, therefore, choose a scenario that encompasses all the crucial elements of the selected topic and present them in an engaging manner.

Demonstrators must incorporate a practical implementation of the attack/defense mechanism/etc. Demonstrators may also be interactive and include additional elements for visualization. Moreover, demonstrators should be easy to set up in a new environment and simple to maintain.

As a thesis topic, the work should also include research about the current state of the art related to the demonstrator as well as documentation and evaluation of test runs and accumulated data of the demonstrator.

List of possible topics:

• Memory attacks and defenses on embedded devices (Master thesis)
• Memory attacks and defenses on desktop machines (Master thesis)
• Intelligent Sensor Networks (Master thesis)
• Middleware Platforms (Master thesis/Bachelor thesis)
• Etc.

If there is a field you are especially interested in you may propose your own topic. Nevertheless, there is no assurance that the proposed topics will be accepted without modifications or accepted at all.
The theses can be written in German or English.