Various security features rely on the assumption that there is a way to store meta data that an attacker cannot access. This requires different measures to make this data unaccusable during normal operation, but accessible when needed in an efficient way. Goal of this thesis is to implement a small instruction set extension that contains dedicated instructions that use a different address translation to support memory isolation on a RISC-V system.

Requirements:

• experience with at least one hardware description language (VHDL, Verilog)
• experience with high level synthesis helpful
• good understanding of memory management and MMU functionality

Supervisor: Kai Lehniger M.Sc. (Kai.Lehniger@b-tu.de)

Return-oriented programming (ROP) is a frequently used technique to exploit stack buffer overflows in applications. The attacker uses existing code snippets that and with a function return, called gadgets, and chains them together to create the desired behaviour. Often times an attacker would like to integrate existing functions into the payload to perform complex operations, for example opening a terminal. Embedding such a function call within a ROP payload is a challenge in itself. For the Xtensa architecture an additional complexity arises due to a special architectural feature: register windows.

Register windows are used to minimize the register save and restore operations at the beginning and end of a function. Instead a large set of physical registers is used, but only parts of it (the register window) is visible to the application. In the beginning of a function, the register window is moved forward to provide the function with new registers, and moved backward at the end.

The goal of this thesis is to correctly incorporating the register window mechanism together with a function call inside a ROP attack.

Requirements:

• proficient C/C++ skills
• basic knowledge about Assembly/hardware architectures
• a good understanding of calling conventions and memory layout

Supervisor: Kai Lehniger M.Sc. (Kai.Lehniger@b-tu.de)

The ESP32 is a microcontroller with various peripherals. One of these peripherals is an AES hardware accelerator that can be used for fast AES encryption and decryption. In a previous work, this hardware accelerator was used to protect register values from being overwritten when they are temporarily stored in the stack, which happens during an interrupt. Open problems to the implementation are the fact that the ESP32 is a dual-core system where multiple cores may want to use the hardware accelerator at the same time and the fact that the application itself may want to use the accelerator itself for other purposes than register value protection.

Commonly applied techniques of access control are not sufficient. Typically, the hardware accelerator can be acquired and released by a task, and other tasks have to wait until the resource is available again. Since the accelerator is now also used in an interrupt, that might interrupt the exact same task that currently uses the accelerator, and the fact that the same interrupt also occurs during a task switch to save register values, makes this method unfeasible without modifications.

The task in this thesis is to adapt the currently used access control scheme to allow the usage of the register protection together with an application that uses the AES accelerator itself, as well as usage in a dual-core context. For this, possible scenarios need to be defined and analysed for deadlocks or corruption of accelerator data. A proof-of-concept access control mechanism needs to be designed, implemented, tested, and evaluated. While most of the parts can be implemented using the C language, the interrupt routines that save and restore register values are written in Assembly.

Requirements:

• proficient C/C++ skills
• basic knowledge about Assembly/hardware architectures
• a very good understanding of access control mechanisms (Module Operating Systems 1)

Supervisor: Kai Lehniger M.Sc. (Kai.Lehniger@b-tu.de)

The elliptic curve point multiplication with a scalar kP is the basic operation in cryptographic protocols for ECC. Binary kP double-and-add algorithms are vulnerable to horizontal side-channel analysis (SCA) attacks. Atomicity and regularity principles are well-known countermeasures against simple SCA attacks assuming that the different register operations cannot be distinguished by their addressing. Modern measurement equipment allows capturing traces with a high sampling rate.  Thus, the register addressing has to be evaluated as the SCA leakage source.
Nowadays, many open-source cryptographic libraries are available for the implementation of cryptographic protocols.
Some of them provide an implementation of the kP operation only. Others provide also mathematical operations in finite fields. Some libraries are claimed to be resistant to one-trace attacks, due to their constant time functions or the kP algorithms implemented corresponding to the regularity or atomicity principles.
The evaluation of the resistance against simple SCA attacks of a selected atomic pattern (or a regular) kP algorithm is the main task of this work. The selected kP algorithm has to be implemented using a selected open-source cryptographic library for an embedded device. The power and/or electromagnetic kP execution traces have to be measured and analyzed.

Possible kP algorithms, for the implementation:

1. B. Chevallier-Mames, M. Ciet, and M. Joye, “Low-cost solutions for preventing simple side-channel analysis: side-channel atomicity,” IEEE Transactions on Computers, vol. 53, no. 6, pp. 760–768, Jun. 2004, doi: 10.1109/TC.2004.13
2. P. Longa, “Accelerating the Scalar Multiplication on Elliptic Curve Cryptosystems over Prime Fields,” Cryptology ePrint Archive, 2008, Accessed: Jul. 13, 2022. [Online]. Available: eprint.iacr.org/2008/100
3. C. Giraud and V. Verneuil, “Atomicity Improvement for Elliptic Curve Scalar Multiplication,” in Proceedings of the 9th IFIP WG 8.8/11.2 International Conference on Smart Card Research and Advanced Application, Berlin, Heidelberg, 2010, pp. 80–101. doi: 10.1007/978-3-642-12510-2_7
4. D. Hankerson, J. Lopez, and A. Menezes, “Software Implementation of Elliptic Curve Cryptography over Binary Fields,” in Cryptographic Hardware and Embedded Systems — CHES 2000, Aug. 2000, pp. 1–24. doi: 10.1007/3-540-44499-8_1
5. K. Itoh, T. Izu, and M. Takenaka, “A Practical Countermeasure against Address-Bit Differential Power Analysis,” in Cryptographic Hardware and Embedded Systems - CHES 2003, Sep. 2003, pp. 382–396. doi: 10.1007/978-3-540-45238-6_30
6. M. Izumi, J. Ikegami, K. Sakiyama, and K. Ohta, “Improved countermeasure against Address-bit DPA for ECC scalar multiplication,” in 2010 Design, Automation Test in Europe Conference Exhibition (DATE 2010), Mar. 2010, pp. 981–984. doi: 10.1109/DATE.2010.5456907

Supervisor: Hon. Prof. Dr.-Ing. Zoya Dyka (dyka@ihp-microelectronics.com)

Side-channel analysis (SCA) and fault injection (FI) attacks are dangerous kinds of physical attacks against cryptographic implementations.

Most often attacked blocks are the registers: their energy consumption for data storing is successfully exploited in vertical SCA attacks and their addressing in horizontal SCA attacks. The values stored in the registers can be manipulated via FI attacks.

Randomized use of redundant hardware blocks can hide at least partially side-channel leakage. At the same time, use of the redundancy can countermeasure fault injection attacks.

Randomized re-arrangement of duplicated and/or triplicated registers during a single cryptographic operation can be a promising approach to reduce the vulnerability of cryptographic implementations to the SCA and FI simultaneously. The implementation of a such flexible redundancy support is especially difficult for cryptographic operations designed as a hardware. The flexible redundancy for registers requires a dynamically (i.e. run-time, or on-the-fly) reconfigurable voter. For ASIC designs only a kind of a pseudo-reconfigurability is possible, i.e. a voter for all reasonable combinations of duplicated and triplicated registers can be used via control signals to support such functionality.

The goals of this investigation are:

• to estimate the area (gate complexity) of the voter supporting all possible combinations of duplicated and triplicated registers for a design with n main and N redundant l-bit long registers on example of small values n, N, and l;
• to estimate the reduction of the area (gate complexity) reducing N as the basis for criterion for determining the reasonable number N of redundant registers for n main registers:
  • the vision is that for the given number n main registers and the given area overhead of X% (from the register’s area) the number of acceptable redundant registers N can be determined.

The estimations have to be performed based on the practical implementation of the voters in VHDL.

An overview of the literature is an important part of the master's thesis.

The following paper can be recommended as an introduction to the topic:

• N. Mentens, "Hiding side-channel leakage through hardware randomization: A comprehensive overview," 2017 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS), Pythagorion, Greece, 2017, pp. 269-272, doi: 10.1109/SAMOS.2017.8344639, https://ieeexplore.ieee.org/document/8344639 (https://www.esat.kuleuven.be/cosic/publications/article-2824.pdf)

Supervisor: Hon. Prof. Dr.-Ing. Zoya Dyka (dyka@ihp-microelectronics.com)

Today, the development and implementation of complex systems rarely carried out by a single manufacturer, who fully manages and controls all development and production steps. This division of labour has clear advantages such as shorter "time-to-market" and reduced costs. It also has the advantage that the necessary competences and tools/machines are focused on core areas. However, the clear disadvantage, is that there are risks associated with the division of labour in terms of product quality (reliability/safety). This also holds true for all aspects of security, leading to the loss of confidentiality, privacy etc. Changes into the product can be made at almost all stages of development and production.

The aim of this master thesis is to develop a methodology and a tool to assess the potential risk of an attack in all stages of development, from initial design to the final product.

Analysing the probability of certain attacks and assessing their severity is a tedious and challenging task. The likelihood of an attack depends on:

• The intention of the potential attacker, which is normally unknown, unless the attack was already executed and the attacker caught. Here typically the following dimension can be considered:
  • type of attack (e.g. espionage, sabotage, or reputational damage)
  • long-term or short-term gain in the view of the attacker
  • the attacker’s position in the supply chain
• The skills an attacker has and the effort he can spend (e.g., time and money)

In this master thesis the following tasks need to be accomplished:

1. Analyse the state of the art in risk assessment
2. Develop a methodology to define the probability that a certain attack will be run in a selected design stage, this methodology needs to provide means to adjust the risk to changing conditions such as motivation and resources of the attacker
3. Implementation of a tool supporting potential user in assessing the attack risks, including a graphical user interface for collecting basic information and displaying the analysis results
4. Evaluation of the tool by applying it to real world use cases e.g. Bloomberg report on potential manipulations of Supermicro PCBs, the Heartbleed bug or similar cases.

An introduction in the problem, including a starting point for the tool development, can be found in the PANDA report:

• https://www.bsi.bund.de/EN/Service-Navi/Publikationen/Studien/PANDA/panda_node.html

Supervisor: Elisabeth Vogel M.Sc. (Elisabeth.Vogel@b-tu.de)

The theses can be written in German or English.

Attack vectors for sensor networks depend on their location of deployment. Sensor nodes in public spaces are easy to access and monitor for a potential adversary and therefore require very effective protection.
The goal of this thesis is to identify threats that are especially likely to occur for sensor networks in publicly accessible spaces and to design a solution that guarantees data integrity and confidentiality for a specific use-case.

Requirements:

• Solid understanding of IT security and wireless sensor networks, including common attack vectors and cryptographic methods.
• Ability to analyze threats and design security solutions tailored to resource-constrained, publicly deployed sensor systems.
• Experience with embedded systems or networked devices and the ability to conduct structured, independent research.

Contact: Elisabeth Vogel M.Sc. (Elisabeth.Vogel@b-tu.de)

Cryptographic operations become a more and more important part in wireless sensor networks (WSNs), be it for secure communication or to authenticate nodes before allowing them to join the network. Provisioning services are typically used during deployment to distribute the necessary security information (keys, certificates, etc.) alongside other information such as location.

Depending on the use cases, nodes may need to be redeployed (repositioning or other reasons), changing the network composition, renewal of certificates, or other reasons, that make re-provisioning necessary. At the same time, WSN nodes are often used in publicly accessible areas, making them susceptible for tampering.

The goal of this thesis is to research existing provisioning methods and design (including a proof-of-concept implementation) a provisioning service for wireless sensor nodes that allows for the distribution of security information only by authorized entities during deployment in the field.

Supervisor: Kai Lehniger M.Sc. (Kai.Lehniger@b-tu.de)

As a potential thesis topic, it is feasible to develop a demonstrator for a specific security topic. A demonstrator serves the purpose of illustrating a topic to an audience. The candidate should, therefore, choose a scenario that encompasses all the crucial elements of the selected topic and present them in an engaging manner.

Demonstrators must incorporate a practical implementation of the attack/defense mechanism/etc. Demonstrators may also be interactive and include additional elements for visualization. Moreover, demonstrators should be easy to set up in a new environment and simple to maintain.

As a thesis topic, the work should also include research about the current state of the art related to the demonstrator as well as documentation and evaluation of test runs and accumulated data of the demonstrator.

List of possible topics:

• Memory attacks and defenses on embedded devices (Master thesis)
• Memory attacks and defenses on desktop machines (Master thesis)
• Intelligent Sensor Networks (Master thesis)
• Middleware Platforms (Master thesis/Bachelor thesis)
• Etc.

If there is a field you are especially interested in you may propose your own topic. Nevertheless, there is no assurance that the proposed topics will be accepted without modifications or accepted at all.
The theses can be written in German or English.