Keyvan Shahin
VG1C, Room 1.18

T: +49 (0) 355 69
F: +49 (0) 355 69 2027

akademischer Mitarbeiter

M.Sc. Keyvan Shahin

Verfügungsgebäude 1C, Raum 1.39

T: +49 (0) 355 69
F: +49 (0) 355 69 2027

Work and Education
  • (2020-now) Research Worker/Ph.D. Student, Brandenburg University of Technology, TECI chair, Cottbus, Germany
  • (2017-2020) Research Worker/Ph.D. Student, Ruhr University of Bochum, ESIT chair, Bochum, Germany
  • (2015-2017) Digital Hardware Designer for Embedded Systems, MECO (MAPNA), Karaj, Iran
  • (2013-2015) Digital Hardware Designer, Aria Wave, Tehran, Iran
  • (2013-2013) Digital System Engineer, SAMA, Tehran, Iran
  • ( 2009-2011 ) M.Sc. Digital Systems. Sharif University of Technology, Tehran, Iran
  • (2004-2009) B.Sc. Electrical Engineering-Electronics, Shahid Beheshti University, Tehran, Iran
Research Interests

Scientific Interests:

  • Hardware Developement on FPGAs and ASICs
  • Hardware/FPGA-Based Acceleration
  • Embedded Systems
  • Communication Hardware Implementation
  • Design Optimization and Design Spcae Exploration
  • DSP Systems Implementation

Available Topics for Students:

Autonomous Drone Swarm:

We are actively seeking individuals who are passionate about contributing to cutting-edge projects, particularly those intrigued by the exciting developments in our iCampus initiative, with a focus on a specialized package named UPWARDS.

Within UPWARDS, our primary objective is to establish a robust framework for orchestrating a swarm of drones to autonomously execute missions. This ambitious endeavor involves the development of a sophisticated middleware that plays a pivotal role in seamlessly transferring sensor data to decision-making units. Simultaneously, the middleware facilitates the transmission of crucial commands between the drones and the ground station.

By joining our team, you'll have the unique opportunity to be at the forefront of drone technology innovation, working on the intricacies of autonomy, data management, and communication systems. If you are enthusiastic about pushing the boundaries of what is possible in unmanned aerial systems, we invite you to explore the possibilities within the iCampus project and contribute to the groundbreaking work we are doing in the UPWARDS package. Your expertise and passion can make a significant impact on the future of autonomous drone missions.

Hardware/FPGA-Based acceleration of floating-point to fixed-point conversion

The realm of Digital Signal Processing (DSP) systems and algorithms relies on the nuanced use of fixed-point and floating-point numeric representations. While general-purpose computers and software-based tools predominantly employ floating-point representation to model and simulate arithmetic operations in DSP systems, the landscape shifts when it comes to implementing hardware solutions, such as Field-Programmable Gate Arrays (FPGAs) or Application-Specific Integrated Circuits (ASICs). In these scenarios, leveraging fixed-point representation often proves markedly more efficient in terms of both area utilization and processing speed.

Despite the prevalence of floating-point representation in software-based tools, the hardware implementation of DSP algorithms necessitates a crucial step: the conversion from floating-point to fixed-point representation. This transformation is pivotal for translating the algorithm's software description into a form conducive to hardware execution. It has been observed that the conversion process, a vital aspect of design, can consume up to 30% of the overall design time, depending on the complexity of the algorithm. Moreover, it can pose a challenging and labor-intensive task for designers.

To date, prevailing approaches for this conversion have been predominantly software-based. While there have been mentions of the potential use of FPGAs to execute this conversion, a comprehensive and methodical framework for a general hardware-based fixed-point simulation has, to the best of our knowledge, been lacking.

This work addresses this gap by introducing a novel FPGA-based hardware framework. This framework incorporates a width-configurable hardware architecture, designed to significantly reduce the execution time of the floating-point to fixed-point conversion process when compared to traditional software-based approaches. By optimizing this critical stage of the design process, our approach not only enhances efficiency but also lays the foundation for advancing the broader field of hardware-accelerated fixed-point simulations in DSP systems.