Im Rahmen des Informatik-Kolloquiums möchten wir Sie recht herzlich zum Institus-Talk

Fostering the use of machine learning on board to satellite: the CloudScout case study and beyond



Luca Fanucci, Space Activities overview at Pisa University and Ingeniars spin-off company
Gianluca Giuffrida, CNN-based on-the-edge clouds detector: the CloudScout case study
Gianmarco Dinelli, FPGA implementation of CloudScout CNN: advantages and disadvantages
Pietro Nannipieri, The ICU4SAT project idea: a Pisa and Brandenburg Universities collaboration
All,  brainstorming

am:                        Mittwoch, 09.12.2020

um:                        15:00 - 16:30 Uhr

                         Meeting number: 121 053 7857  Password: 99sTN33kcRM


Fostering the use of machine learning on board to satellite: the CloudScout case study and beyond
Machine Learning (ML) has already demonstrated its capability to solve complex problem in the cloud. With the advancement of dedicated embedded hardware accelerators, the potential of ML can be exploited also at the edge. This opens very interesting scenarios also for space applications, both for communication/control and payload levels. In fact, at control level ML algorithms can be exploited to control the navigation of satellites, using images of target planets or moon craters as reference points. At payload level, instead, ML can be used to simplify Earth Observation for remote sensing applications, directly elaborating data on-board reducing the dependency with the earth: such as cloud detection, fire detection, object detection, land cover / land use classification, etc. For these image-based scenarios Convolutional Neural Networks (CNNs) and theirs derivates represent one of the most promising algorithms.
This seminar will present some research activities on CNN-based algorithms for embedded and low power platforms at the edge recently developed at the University of Pisa. Starting from the CloudScout CNN recently launched on board of the Phisat-1 mission we will discuss several trade-off in terms of output accuracy, power consumption and memory requirements for commercial (e.g. Intel Movidius Myriad-2) and dedicate hardware accelerators based on FPGA. Finally we will present the concept of the Instrumentation Control Unit for Satellite Application (ICU4SAT) project to be developed in collaboration with Brandenburg University of Technology – Cottbus-Senftenberg.

Speakers Short Bio

Luca Fanucci (Fellow, IEEE) received the Laurea and Ph.D. degrees in electronic engineering from the University of Pisa in 1992 and 1996, respectively. From 1992 to 1996, he was a Research Fellow with the European Space Agency (ESTEC), Noordwijk, The Netherlands. From 1996 to 2004, he was a Senior Researcher with the Italian National Research Council, Pisa. He is currently a Professor of microelectronics with the University of Pisa. His research interests include several aspects of design technologies for integrated circuits and electronic systems, with particular emphasis on system-level design, hardware/software co-design and sensor conditioning, and data fusion, and also wireless communications, low-power multimedia, automotive, healthcare, ambient assisted living, and technical aids for independent living. He is the coauthor of more than 400 journal articles and conference papers and a co-inventor of more than 40 patents. He is a member of the Editorial Board of Technology and Disability (IOS Press) Journal. He has served in several technical programme committees of international conferences. He was the Program Chair of DSD 2008 and DATE 2014 and the General Chair of DATE 2016 and HiPEAC 2020.

Gianluca Giuffrida got the bachelor’s degree in computer engineering at the Università degli studi di Catania in 2015. He got the master’s degree in Embedded Computing System at the University of Pisa in 2018. Master’s thesis work was based on an autonomous robotic arm for people with disabilities exploiting machine learning algorithms for object detection. He is currently pursuing the PhD in Information Engineering at the University of Pisa where main research topics are Machine Learning, Artificial Intelligence, Computer Vision and Robotics. Gianluca led the development team of the CloudScout convolutional neural network which was launched on 3 September 2020 on board to the Phisat-1 mission.

Gianmarco Dinelli received the M.Sc. degree (110 cum laude) in electronic engineering from the University of Pisa, where he is currently pursuing the Ph.D. degree with the VLSI Lab, Department of Information Engineering. His work is mainly related to digital system design, from system specifications to hardware implementation on an FPGA device. His research interests include satellite on-board data-handling subsystem and on the design of FPGA-based hardware accelerators for machine learning algorithms (e.g. CNNs), with particular attention to low power and resource-constrained on-the-edge applications.

Pietro Nannipieri got his Ph.D. in Information Engineering from University of Pisa in 2020 cum laude. His interests are digital and VLSI design as well as electronics for space applications. Pietro spent several Months in 2019 as Visiting Researcher in the TEC-EDP Section in ESTEC (ESA), where he carried out different qualification test on the SpaceFibre technology. He is currently a Post-doc researcher in the VLSI lab of the information engineering department, University of Pisa. His work mainly focuses on the development of IPs for satellite on-board data handling, (i.e. SpaceFibre), but also on signal processing and hardware cryptography.


Im Rahmen des Informatik-Kolloquiums möchten wir Sie recht herzlich einladen zum Vortrag von Frau Dr. Alexandra Kourfali (Universität Ghent, Belgien)


zum Thema:      Novel Hardware Verification Methods for FPGAs”


am:                        Montag, 02.03.2020

um:                        11:00 Uhr

im:                          Verfügungsgebäude 1C, Raum 1.24

Due to the continuously shrinking transistor sizes, anomalies are caused in the design that needs contingency plans. These contingency plans need to be available as soon as possible in the design of an IC, to avoid costly redesigns and other associated delays. Additionally, as the number of transistors inside ICs increases, thus allowing more complex digital designs to be realized, debugging and verifying these designs has become an increasingly difficult task. Moreover, multiple designs contain a safety-critical feature. They are in need to comply with specific safety-critical standards, making IC reliability a fundamental concern in the design and manufacturing process. Various hardware verification techniques exist, that can be used based on the requirements of each design and at different stages in the design flow. There is a trade-off between speed, design complexity, internal signal observability, and required fault coverage.

This talk will address these issues, and discuss the creation of verification methods that cover bugs, permanent faults, and soft errors. With interest in commercial SRAM-based FPGAs, this talk addresses the problems of providing continuous operation after an error occurred by achieving a runtime reconfigurable recovery from a failure, and to ensure that bugs that have escaped pre-silicon validation are detected. In particular, emulation-based verification techniques that are dependent on a long verification cycle and need significant resources are addressed throughout the talk, namely fault injection, fault tolerance, and in-circuit debugging.
The objectives for this work are focused on providing novel methods, tools, and design techniques for hardware verification that can be either applied for FPGA prototyping during ASIC verification or when an FPGA is the final product. They address major industry bottlenecks, namely area and time overhead, limited internal observability, long recompilation/reconfiguration times, and intolerance to soft errors and other radiation effects.

Zum Kolloquium am Montag, dem 13.01.2020, laden wir alle Interessenten recht herzlich ein.

Prof. Paolo Rech, Universidade Federal do Rio Grande do Sul (Brasilien)
spricht zum Thema:
Reliability of Computing Systems in the Era of Autonomous Vehicles and Supercomputers

Termin: 10:00 Uhr
Raum:    Verfügungsgebäude 1C, Seminarraum 0.01

Reliability is one of the major concerns for both safety-critical and High-Performance Computing applications. A neutron impact can generate faults in computing devices, leading to application crashes, wrong results, and system hangs. Several evidence showed that neutron-induced faults have corrupted large-server operations, have caused unexpected behaviours in airplanes, lead to car accidents, and even influenced politics results. In the talk we will briefly cover the effects of neutron impact on computing systems and applications. Particular emphasis will be given to self-driven cars, which is the newest trend in the automotive industry. We will present the results of several experiments on object-detection frameworks for automotive applications and show that neutrons can effectively change the way a vehicle senses objects, potentially leading to accidents. Lately, novel architectural solutions, such as heterogeneous computing and mixed-precision architectures, have been introduced to increase devices computational efficiency. We will discuss if and how we can take advantage of these novel architectural solutions to improve applications' reliability without unnecessary overhead. Particular attention will be given to the reliability of Xilinx Field-Programmable Gate-Arrays (FPGA), Intel Xeon Phis, NVIDIA Graphics Processing Units (GPUs), ARM embedded devices, and AMD heterogeneous devices.

Zum Kolloquium am Montag, dem 09.12.2019, laden wir alle Interessenten recht herzlich ein.

Prof. José Rodrigo Azambuja, Universidade Federal do Rio Grande do Sul (Brasilien)
spricht zum Thema:
Fault Tolerance Techniques for Graphics Processing Units

Termin: 15:30 Uhr
Raum:    Verfügungsgebäude 1C, Seminarraum 0.01

Graphics Processing Units (GPUs) have evolved from devices specially designed for graphics rendering to general-purpose accelerators for High-Performance Computing (HPC) applications and, more recently, to expedite the training and execution of Deep Learning frameworks. Artificial Neural Networks (ANNs) are becoming a widely adopted computational approach in many fields, such as data mining, pattern recognition, robotics, data analytics. Lately, ANNs have been extensively used to detect objects in a scene in realtime, an essential function in modern  autonomous vehicles. As GPUs moved in HPC and safety-critical domains, questions about their  reliability started to raise. This talk discusses the use of selective fault tolerance techniques and approximate computing to harden such devices.

Zum Kolloquium am Montag, dem 2. Dezember 2019, laden wir alle Interessenten recht herzlich ein.

 Prof. Dr. Martin Ziegler (KAIST School of Computing, Daejeon, South Korea)

spricht zum Thema:

Computer Science for Numerics

Beginn:  13:45 Uhr
Ort:   Lehrgebäude 1 A, Raum 304

Since introduction of the IEEE 754 floating point standard in 1985, numerical methods have become ubiquitous - and increasingly sophisticated.
With growing code complexity of numerical libraries grows the need for rigorous Software Engineering methodology: as provided by Computer Science and
state of the art regarding digital processing of discrete data, but lacking in the continuous realm.
We apply, adapt, and extend the classical concepts - specification, algorithmics, analysis, complexity, verification - from discrete bit strings, integers, graphs etc.
to real numbers, converging sequences, smooth/integrable functions, bounded operators, and compact subsets.
A new paradigm bridged between the BSS model and Computable Analysis.
It formalizes mathematical structures as continuous abstract data types with rigorous computable semantics.

Following the last decades' seminal interplay between Discrete Mathematics and Computer Science,
Future Numerics revolves around Computer Science bridging between Pure and Applied continuous Mathematics.


Zum Kolloquium am Montag, dem 25.11.2019, laden wir alle Interessenten recht herzlich ein.

 Prof. Antonio Beck, Universidade Federal do Rio Grande do Sul (Brasilien)
spricht zum Thema:
Adaptability – The Key for Future (Embedded?) SystemsAbstract

Termin: 15:30 Uhr
Raum:   Lehrgebäude 1A, Raum 304

Most traditional hardware architectures are based on a fixed design that limits its run-time adaptability. Therefore, these platforms are unable to cope with the varying application behavior when one considers non-functional requirements that are increasing in importance, such as fault tolerance, power, energy, or even quality. In this context, this talk will discuss several approaches to adapting the hardware dynamically to the application at hand and deliver the best trade-off among these non-functional requirements, according to a given set of design choices