Im Rahmen des Informatik-Kolloquiums möchten wir Sie recht herzlich einladen zum Vortrag von Frau Dr. Alexandra Kourfali (Universität Ghent, Belgien)


zum Thema:      Novel Hardware Verification Methods for FPGAs”


am:                        Montag, 02.03.2020

um:                        11:00 Uhr

im:                          Verfügungsgebäude 1C, Raum 1.24

Due to the continuously shrinking transistor sizes, anomalies are caused in the design that needs contingency plans. These contingency plans need to be available as soon as possible in the design of an IC, to avoid costly redesigns and other associated delays. Additionally, as the number of transistors inside ICs increases, thus allowing more complex digital designs to be realized, debugging and verifying these designs has become an increasingly difficult task. Moreover, multiple designs contain a safety-critical feature. They are in need to comply with specific safety-critical standards, making IC reliability a fundamental concern in the design and manufacturing process. Various hardware verification techniques exist, that can be used based on the requirements of each design and at different stages in the design flow. There is a trade-off between speed, design complexity, internal signal observability, and required fault coverage.

This talk will address these issues, and discuss the creation of verification methods that cover bugs, permanent faults, and soft errors. With interest in commercial SRAM-based FPGAs, this talk addresses the problems of providing continuous operation after an error occurred by achieving a runtime reconfigurable recovery from a failure, and to ensure that bugs that have escaped pre-silicon validation are detected. In particular, emulation-based verification techniques that are dependent on a long verification cycle and need significant resources are addressed throughout the talk, namely fault injection, fault tolerance, and in-circuit debugging.
The objectives for this work are focused on providing novel methods, tools, and design techniques for hardware verification that can be either applied for FPGA prototyping during ASIC verification or when an FPGA is the final product. They address major industry bottlenecks, namely area and time overhead, limited internal observability, long recompilation/reconfiguration times, and intolerance to soft errors and other radiation effects.

Zum Kolloquium am Montag, dem 13.01.2020, laden wir alle Interessenten recht herzlich ein.

Prof. Paolo Rech, Universidade Federal do Rio Grande do Sul (Brasilien)
spricht zum Thema:
Reliability of Computing Systems in the Era of Autonomous Vehicles and Supercomputers

Termin: 10:00 Uhr
Raum:    Verfügungsgebäude 1C, Seminarraum 0.01

Reliability is one of the major concerns for both safety-critical and High-Performance Computing applications. A neutron impact can generate faults in computing devices, leading to application crashes, wrong results, and system hangs. Several evidence showed that neutron-induced faults have corrupted large-server operations, have caused unexpected behaviours in airplanes, lead to car accidents, and even influenced politics results. In the talk we will briefly cover the effects of neutron impact on computing systems and applications. Particular emphasis will be given to self-driven cars, which is the newest trend in the automotive industry. We will present the results of several experiments on object-detection frameworks for automotive applications and show that neutrons can effectively change the way a vehicle senses objects, potentially leading to accidents. Lately, novel architectural solutions, such as heterogeneous computing and mixed-precision architectures, have been introduced to increase devices computational efficiency. We will discuss if and how we can take advantage of these novel architectural solutions to improve applications' reliability without unnecessary overhead. Particular attention will be given to the reliability of Xilinx Field-Programmable Gate-Arrays (FPGA), Intel Xeon Phis, NVIDIA Graphics Processing Units (GPUs), ARM embedded devices, and AMD heterogeneous devices.

Zum Kolloquium am Montag, dem 09.12.2019, laden wir alle Interessenten recht herzlich ein.

Prof. José Rodrigo Azambuja, Universidade Federal do Rio Grande do Sul (Brasilien)
spricht zum Thema:
Fault Tolerance Techniques for Graphics Processing Units

Termin: 15:30 Uhr
Raum:    Verfügungsgebäude 1C, Seminarraum 0.01

Graphics Processing Units (GPUs) have evolved from devices specially designed for graphics rendering to general-purpose accelerators for High-Performance Computing (HPC) applications and, more recently, to expedite the training and execution of Deep Learning frameworks. Artificial Neural Networks (ANNs) are becoming a widely adopted computational approach in many fields, such as data mining, pattern recognition, robotics, data analytics. Lately, ANNs have been extensively used to detect objects in a scene in realtime, an essential function in modern  autonomous vehicles. As GPUs moved in HPC and safety-critical domains, questions about their  reliability started to raise. This talk discusses the use of selective fault tolerance techniques and approximate computing to harden such devices.

Zum Kolloquium am Montag, dem 2. Dezember 2019, laden wir alle Interessenten recht herzlich ein.

 Prof. Dr. Martin Ziegler (KAIST School of Computing, Daejeon, South Korea)

spricht zum Thema:

Computer Science for Numerics

Beginn:  13:45 Uhr
Ort:   Lehrgebäude 1 A, Raum 304

Since introduction of the IEEE 754 floating point standard in 1985, numerical methods have become ubiquitous - and increasingly sophisticated.
With growing code complexity of numerical libraries grows the need for rigorous Software Engineering methodology: as provided by Computer Science and
state of the art regarding digital processing of discrete data, but lacking in the continuous realm.
We apply, adapt, and extend the classical concepts - specification, algorithmics, analysis, complexity, verification - from discrete bit strings, integers, graphs etc.
to real numbers, converging sequences, smooth/integrable functions, bounded operators, and compact subsets.
A new paradigm bridged between the BSS model and Computable Analysis.
It formalizes mathematical structures as continuous abstract data types with rigorous computable semantics.

Following the last decades' seminal interplay between Discrete Mathematics and Computer Science,
Future Numerics revolves around Computer Science bridging between Pure and Applied continuous Mathematics.


Zum Kolloquium am Montag, dem 25.11.2019, laden wir alle Interessenten recht herzlich ein.

 Prof. Antonio Beck, Universidade Federal do Rio Grande do Sul (Brasilien)
spricht zum Thema:
Adaptability – The Key for Future (Embedded?) SystemsAbstract

Termin: 15:30 Uhr
Raum:   Lehrgebäude 1A, Raum 304

Most traditional hardware architectures are based on a fixed design that limits its run-time adaptability. Therefore, these platforms are unable to cope with the varying application behavior when one considers non-functional requirements that are increasing in importance, such as fault tolerance, power, energy, or even quality. In this context, this talk will discuss several approaches to adapting the hardware dynamically to the application at hand and deliver the best trade-off among these non-functional requirements, according to a given set of design choices

Vom 09.09.-13.09.2019 findet in Cottbus die Tagung Declare 2019 zur Deklarativen Programmierung bestehend aus folgenden Events statt:

  WLP 2019 - 33rd Workshop on
     (Constraint) Logic Programming,
  WFLP 2019 - 27th International Workshop on
     Functional and Logic Programming  und
  INAP 2019  - 22nd International Conference on Applications of
     Declarative Programming and Knowledge Management


Zum Kolloquium am Donnerstag, dem 13.06.2019, laden wir alle Interessenten recht herzlich ein.

 Prof. Fabian Vargas, Catholic University – PUCRS, Porto Alegre, Brasilien spricht zum Thema:
„Recent research topics in the Signals & Systems for Computing (SiSC) Group“

Termin: 14:30 Uhr
Raum: Verfügungsgebäude, Seminarraum 0.01

The presentation is split in two parts. First, we address research on the development of a combined ionizing radiation & electromagnetic interference test procedure to achieve reliable integrated circuits. Then, in the second part, we focus research on the development of  a new approach to support mixed-criticality workload execution and a fault-free task scheduling algorithm in a multicore processor-based embedded system.

Part I: International standards have been proposed and used to test Integrated Circuits (ICs) for Total-Ionizing Dose (TID) and Single-Event Upset (SEU) as well as for Electromagnetic Interference (EMI). Nevertheless, these standards are separately applied to the IC or electronic system, one after the other, and do not take into account the combined effects of these types of radiation may take over the ICs. In more detail, there is no standard that rules combined tests for TID, SEU and EMI. This topic addresses this lack of product quality information and develop a new methodology to improve the reliability of ICs by performing combined tests for TID, SEU and EMI. We also present recent experimental results from combined measurements we performed on a commercial FPGA IC widely used in critical embedded applications such as aerospace and automotive.
Such results strongly suggest that the effects of radiation are not negligible and should be taken into account if one intends to design reliable embedded systems.

Part II: Recently, the use of multicore processors in general-purpose real-time embedded systems has experienced a huge increase. Unfortunately, critical applications are not benefiting from this type of processors as one could expect. The major obstacle is that we may not predict and provide any guarantee on real-time properties of software running on such platforms. The shared memory bus is among the most critical resources,
which severely degrades the timing predictability of multicore software due to the bus access contention between cores. This part of the talk presents the current research state on a new approach to support mixed-criticality workload execution in a multicore processor-based embedded system. The approach is based on the use of an infrastructure intellectual property (I-IP) core named Deadline Enforcement Checker (DEC), implemented in hardware, which automatically manages the execution of any number of cores in a TDMA-based bus access police while guaranteeing critical task schedulability. This approach allows the exploitation of the maximum performance offered by a multiprocessing system while guaranteeing critical task schedulability, i.e., that the critical task execution will not violate timing deadline. A case-study based on a quad-core version of the LEON3 softcore processor was implemented in VHDL language. Practical experiments demonstrate the proposed technique is very effective on combining system high performance with critical task schedulability within timing deadline. We also present a second functionality of the DEC I-IP, which aims at monitoring the scheduling process in an Operating System (OS). A preliminary case-study is under implementation, where the OS is running the Early Deadline First (EDF) task scheduling algorithm. The goal of the DEC I-IP, in this case, is to detect faults that escape detection by the native fault detection mechanisms embedded in the OS kernel.



Zum Kolloquium am Dienstag, dem 28.05.2019 laden wir alle Interessenten recht herzlich ein.

Dipl.-Inf. Thomas Prescher und Dipl.-Inf. Julian Stecklina von der Cyberus Technology GmbH aus Dresden sprechen zum Thema:
"LazyFP: Discovering Side-Channels is not a Beach Vacation"

Termin: Dienstag, 28.05.2019  15:30 Uhr
Raum: ZHG, Hörsaal C


In 2018, we jointly discovered and responsibly disclosed the LazyFP microarchitectural side-channel vulnerability (CVE-2018-3665). LazyFP is a Meltdown-type attack on hypervisors and operating systems that use lazy FPU context switching and allows recovery of FPU/SSE/AVX register sets across process and virtual machine boundaries. The underlying microarchitectural flaw is present in all modern Intel Core-based processors.

In this talk, we look at this vulnerability in two ways. On the technical side, we review the different register sets on an x86 CPU and how operating system kernels and hypervisors manage them. We describe how the obscure Lazy FPU context switching optimization together with a microarchitectural weakness form an information disclosure vulnerability. We explain why FPU registers can even contain interesting secrets and how this vulnerability was mitigated.

On the non-technical side, we tell the story of two systems developers working for different companies, one at a small German cyber-security company and one at an American trillion-dollar corporation, finding a security issue in Intel's main product. Looking back on these turbulent events, we detail our personal lessons learned and how we would approach an event like this in the future.

Einladung mit Abstract

Abschiedsvorlesung von Prof. Dr.-Ing. Heinrich Theodor Vierhaus

In seiner Abschiedsvorlesung spricht Prof. Dr.-Ing. Heinrich Theodor Vierhaus (Lehrstuhl Technische Informatik) zum Thema:

Zuverlässige Elektronik-Systeme aus unzuverlässigen Komponenten

Termin: Freitag, 26.10.2018 um 13:30 Uhr
Raum: Hörsaal A im Zentralen Hörsaalgebäude

Alle Interessenten sind recht herzlich eingeladen.

44th International Workshop on Graph-Theoretic Concepts in Computer Science

Erster Platz beim Lausitzer WissenschaftsTransferpreis 2018 für Kooperationsprojekt vom LS RNKS und LEAG

Über den ersten Preis und ein Preisgeld von 5.000 € können sich der Lehrstuhl Rechnernetze und Kommunikationssysteme und die Lausitzer Energie Kraftwerke AG freuen. Im Projekt »IT-Sicherheit der digitalen Prozessleit- und Prozessrechensysteme« setzen sich die IT-Spezialisten von BTU und LEAG mit der Sicherheit von kritischen Infrastrukturen auseinander. In den Projekten SICIA und INDI wurden passive Schutzmethoden entwickelt, die Netzdaten auf Anomalien untersuchen und eine Grundlage für das Einleiten weiterer Sicherheitsmaßnahmen liefert.

Quelle: Pressemitteilung der BTU Cottbus - Senftenberg vom , Pressemitteilung der Wirtschaftsinitiative Lausitz e.V. vom 24.04.2018

Projektseiten: SICIA (Security Indicators for Critical Infrastructure Analysis), INDI (Intelligent Intrusion Detection Systems for Industrial Networks)

Testen von Software - ein Praxisbericht

Am Dienstag, den 30.01.2018 findet 11:30-13.00 im VG1c, R 2.01 im Rahmen der Vorlesung ‘Testen von Software’ ein Vortrag zum Thema: Testen von Software - ein Praxisbericht statt, gehalten von Herrn Daniel Scheibler Fachbereichsleiter Verifikation & Validierung Firma PHILOTECH Systementwicklung und Software GmbH.

Alle Interessenten sind herzlichst eingeladen.


Nach einer kurzen Vorstellung der Tätigkeitsfelder der Firma Philotech, werden insbesondere die Anforderungen an die Erstellung und den Test von Software für funktional sicherheitskritische Systeme und Anwendungen exemplarisch diskutiert. Für die Entwicklung eines safety-relevanten Produktes, sind neben technischen Aspekten und Anforderungen an die Software immer auch die Vorgehensweise und die Dokumentation von Bedeutung.

Neben der systematischen Dokumentation von Anforderungen und der Implementierung, sind umfangreiche qualitätssichernde Aktivitäten wie Testen und die Durchführung von Reviews notwendig.

Von der systematischen Erfassung der Anforderungen an die Software bis zum Qualitäts- und Konfigurationsmanagement gibt es diverse Maßnahmen für eine sicherheitsgerichtete Software-Entwicklung, die im Projektverlauf implementiert werden müssen.

Dieser Vortrag erläutert anhand von Beispielen aus Luftfahrt- und Automobilindustrie, welche gängigen Vorgehensweisen aktuell etabliert sind und gibt einen Überblick über die Durchführung von sicherheitsgerichteten Entwicklungsprojekten.

Die Entdecker der Computer-Sicherheitslücken Spectre und Meltdown gewähren einen Blick hinter die Kulissen

Vortrag von Thomas Prescher und Werner Haas.

Dienstag, 23.01.2018, 17:00 - 19:00 Uhr im Hörsaal A des zentralen  Hörsaalgebäudes (ZHG).

Video-Mitschnitt des Vortrages bei YouTube.

Weitere Informationen: siehe Pressemitteilung der BTU Cottbus-Senftenberg

Informatik-Kolloquium am FG Sichere Softwaresysteme

Zum Kolloquium am Montag, dem 24.04.2017 laden wir alle Interessenten recht herzlich ein.

Herr Dr. Jan Sürmeli von der Technischen Universität Berlin spricht zum Thema:

"Achieving Transparency and Auditability in Identity Management with Distributed Ledgers"

Termin: Mittwoch, 24.04.2017  13:30 Uhr
Raum: VG1C, Seminarraum 2

Einladung (Abstract)

10. Alumnitreffen der IT-Studiengänge

Das 10. Alumni-Treffen findet am 27. Mai 2016 ab 14:00 in ZHG HS C statt.

Weitere Informationen auf den Alumni-Seiten.

Informatik-Kolloquium am Fachgebiet Programmiersprachen und Compilerbau

Zum Kolloquium am Mittwoch, dem 24.02.2016 laden wir alle Interessenten recht herzlich ein.

Herr Prof. Dr. Stefan-Alexander Schneider, Lehrgebiet Grundlagen der Fahrerassistenzsysteme, Hochschule Kempten, spricht zum Thema:

"IT as Enabler for Advanced Driver Assistance Systems"

Termin: Mittwoch, 24.02.2016  9:00 Uhr
Raum: Hauptgebäude 0.18


Informatik-Kolloquium am Fachgebiet Theoretische Informatik

Zum Kolloquium am Donnerstag, dem 29. Januar 2016 von 11.30 bis 13.00 Uhr, Hauptgebäude, Raum 0.18, laden wir alle Interessenten recht herzlich ein.

Herrn Prof. Dr. Daniel Merkle, University of Southern Denmark, Odense, Dänemark, spricht zum Thema:

"Exploration and Analysis of Chemical Spaces"

Termin: Freitag, 29.01.2016 11.30 – 13.00 Uhr
Raum: Hauptgebäude, Raum 0.19

Novel methods to model chemistry on an atomic level with algebraic and graph rewriting approaches will be presented. We use a formalism, rooted in category theory, called the Double Pushout approach, which directly expresses the transition state of chemical reactions.

Chemical spaces generated by graph grammars contain important transformation patterns such as so-called autocatalytic sub-networks or alternative routes to molecules of interest. Such chemical motifs are usually hard to find due to the computational complexity of the underlying problem and the vastness of the chemical spaces.

However, our algorithmic approaches combined with the explicitness of our models allow for detailed investigations within these spaces, which is the foundation for understanding function of biological systems. Furthermore, direct wet lab experimental design, verification, and refinement are possible. Results for selected chemical systems will be given.

Informatik-Kolloquium am Lehrstuhl Theoretische Informatik

Zum Kolloquium am Donnerstag, dem 26. November 2015 von 15.30 bis 17.00 Uhr, Hauptgebäude, Raum 0.18, laden wir alle Interessenten recht herzlich ein.

Herr Prof. Dr. Luis Miguel Pardo, Universidad den Cantabria Santander (Spanien), spricht zum Thema:

"On Smale's 17th Problem: a survey"

Termin: Donnerstag, 26.11.2015 15.30 – 17.00 Uhr
Raum: Hauptgebäude, Raum 0.18

In this talk I will survey the main contributions that lead to a complete solution of Smale's 17th Problem. Smale's 17th Problem was stated as follows:
"Can a zero of n complex polynomial equations in n unknowns be found approximately, on the average, in polynomial time with a uniform algorithm?"

Mehr Informationen zu den Smaleschen Problemen finden sich auf Wikipedia:'s_problems

Umzug des Instituts für Informatik, Informations- und Medientechnik

Das Instituts für Informatik, Informations- und Medientechnik der Cottbus-Senftenberg ist größtenteils in das neue Verfügungsgebäudes 1C umgezogen.

Neue Adresse:
Verfügungsgebäude 1C
Konrad-Wachsmann-Allee 5
03046 Cottbus

Umgezogen sind die Fachgebiete:

  • Datenbanken und Informationssysteme
  • Datenstrukturen und Softwarezuverlässigkeit
  • Graphische Systeme
  • Internet - Technologie
  • Programmiersprachen und Compilerbau
  • Rechnernetze und Kommunikationssysteme
  • Sichere Softwaresysteme
  • Software-Systemtechnik
  • Technische Informatik
  • Sicherheit in pervasiven Systemen
  • Systeme [gemeinsame Berufungen mit dem IHP in Frankfurt/Oder).

Die Fachgebiete Theoretische Informatik und Verteilte Systeme/Betriebssysteme verbleiben im Hauptgebäude.

Informationen und Bilder finden Sie auf der Webseite zum Neubau.

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