„ARC 2023 - The 19th International Symposium on Applied Reconfigurable Computing”

Im Rahmen der am FG Technische Informatik stattfindenden internationalen ARC-Konferenz möchten wir Sie recht herzlich zum Vortrag von
 

Herrn Dipl. Ing. Paul Blinzer (Fellow System SW, AMD Inc., USA) keynote

zum Thema       "The Flexibility Conundrum – Custom Accelerators vs Common Software"

einladen.

Termin:    27.09.2023, 09:00-10:00 Uhr
Ort:          Verfügungsgebäude 1C, SR 0.01

Abstract

With ever more demand for compute performance and large dataset processing for machine learning, high performance compute and other domains, efficiently integrating sophisticated, custom accelerators into established large application frameworks that initially were focusing on host CPU processing becomes ever more challenging.

The presentation outlines existing challenges and outlines ongoing work in the AMD Research and Advanced Development work on explorations to simplify integration of scalable custom domain accelerator functionality into well-established, low overhead application programming models.

Vita

Mr. Paul Blinzer is a Fellow at AMD in the Platform Software Group, has contributed on a wide range of technologies over his 24 years at AMD and holds over 40 issued patents. His most recent area of work leverages the capabilities of advanced data fabrics, accelerators and CPUs into application and operating system programming models. He is participating in workgroups of several standards organizations and was serving as the Chairperson of the System Architecture Workgroup of the HSA Foundation.

Mr. Blinzer lives in the Seattle/WA area, enjoys working on the forefront of technology and many outdoor activities, in accordance to the assumptions about the general lifestyle in the Pacific Northwest of the United States.


Blockveranstaltung „Compiler design and implementation for energy efficient embedded systems”

11.09.2023 - 15.09.2023, 10:00 – 12:00 Uhr

Vortragender: Prof. Dr. Pedro Diniz, Universität Porto (Portugal)

Ort: Zentralcampus, Verfügungsgebäude 1C, SR 0.01

Abstract

This short Compilers Design and Implementation course is intended to give the students an overview of the organization of traditional compilers for modern computer programming languages. This course briefly covers the classical phases of parsing, internal representation, code generation as well as optimization, for speed and energy-efficiency, and time permitting also describing the basics of advanced topics such as data-flow analysis and control-flow analysis, and optimization. Students are expected to know basic concepts of imperative programming languages such as syntax, scoping and semantics as well as understand basic computer architecture and organization. This short course is structured as five 2-hour lectures with daily take-home review exercises with solutions to illustrate the application of various analysis and compiler algorithms and implementations.

Organisiert vom Fachgebiet Technische Informatik.

Bei Interesse bitte Rückmeldung an kathleen.galke(at)b-tu.de


Informatik-Kolloquium

im Rahmen des Informatik-Kolloquiums möchten wir Sie recht herzlich zum Vortrag von
 

Herrn Prof. Dr. Günther Wirsching (Katholische Universität Eichstätt-Ingolstadt)


zum Thema       "Quantum-Inspired Logic"
einladen.

Termin:    11.07.2023, 10:00 Uhr

Ort:         ZHG, Hörsaal B <- Achtung: Raumänderung!

Abstract

Starting with mathematical models for human cognition, we consider mathematical structures connected to logic, with references to Aristotle, Boole, Birkhoff, and von Neumann. Based on this, we characterize probabilistic extensions of classical logics and contrast them with fuzzy logic. The logic of quantum mechanics provides a structure where all probabilistic logics are substructures or special cases, and which, moreover, contains extensions which open the way to further applications. We indicate some applications of quantum-inspired logic in the context of databases and psychology. Finally, we present quantum-inspired aspects of signal representation and vector symbolic architectures.