Concepts for ultra high speed end-to-end protocol processing at data rates of 100 Gbit/s and beyond.

  • Duration: November 2014 bis October 2016
  • Funding: DFG Project
  • Partner: Prof. Rolf Kraemer, FG Systeme, BTU Cottbus-Senftenberg

Wireless ultra-high speed communication is currently a big driver of new challenging applications. Media distribution is one of the most data-rate demanding applications that require real multi- gigabit per second (Gb/s) streams. Even today, a 3D-HDTV film contains up to 50 GByte, despite the application of most recent source encoding technologies. In the next years, systems providing increased image resolutions will be introduced. The Japanese SuperHiVision system, expected to enter the market around the year 2020, is based on a sampling scheme with 7680 x 4320 pixels at 60 frames per second, leading to raw data rates of 72 Gb/s. In several production processes, a wireless transmission of such data rates will be required. Another application of fast wireless links is the distribution of media, e.g. via kiosk systems, where huge data files have to be transmitted in a few seconds. Even the distribution of the content stored on one of today’s BluRay discs is a task, which cannot be solved using existing communication technologies. 
This ultra-high transmission rates have to be accessible on the application layer, thus we need end-to-end communication support. This is the main driver for the End2End100 project proposal. Several challenges and unsolved research questions arise from the idea of wireless 100Gb/s transmission, which are the focus of the special priority program “Wireles100Gb/s and Beyond”. We will address the questions of the MAC protocol processor to receive a raw data stream, and forward it to the correct application processors. We will concentrate on MAC and PHY parallelization issues knowing that also on higher protocol levels open questions need to be addressed. We consider, however, a single-hop wireless scenario, i.e. with end-to-end transmissions. This scenario covers, for instance, the potential media kiosk applications, mentioned previously, based on short-range wireless links. Therefore, it is justified that we do not address problems of the network layer (IP) and transmission layer (TCP).

The End2End100 project works closely together with other proposed projects of the priority program SPP1655, e.g. the Real100G.com and Real100G.RF. This group of projects, even if not mutual dependent on each other, will investigate a complete wireless 100Gb/s system with a moderate bandwidth efficiency at ultra-high frequencies (250-330GHz), and a huge bandwidth (50GHz). The results of the End2End100 project will also be useful for other projects, although interfaces and aspects of PHY-MAC interaction might slightly differ. Our main technical idea is to investigate an innovative concept for a network interface card (NIC) that concentrates all end-to-end activities. We split the research efforts into three major areas:

  • Parallel Protocol Processing Due to huge data rates, MAC-processing requires a powerful processor system. In our case, we plan to investigate to what extent a parallel processing system, based on a many- core processor architecture, provides benefits for a NIC supporting wireless 100 Gb/s. Moreover, we will examine how to parallelize the protocol processing and amend it with special hardware accelerators.
  • MAC Core State machines The protocol engine mainly controls the data streams in both directions, to and from the application side, and to and from the air-interface. This requires intelligent error correction and flow control schemes, leading to complex state machines with ultra-high speed requirements. Clearly, these complex state machines affect the final MAC architecture, which requires a high level of parallelization (i.e. handling of a single MAC-stream by more than one processor core) and hardware/software partitioning (i.e. use of hardware accelerators for certain MAC functions).
  • Error correction schemes of the MAC-PHY processing Since wireless transmission can suffer from extremely high bit-error rates (BER), we will examine the channel impact and the adequate error correction mechanism (FEC/ARQ) trade-off. On the one side, wireless communication needs a certain degree of redundancy, for instance an appropriate forward error correction scheme to reduce the bit error probability. On the other side, this redundancy reduces the overall throughput, as it results in more transmitted bytes and more processing on both senders and receivers.



  • L. Lopacinski, M. Brzozowski, R. Kraemer, S. Buechner, and J. Nolte, "100 Gbps data link layer - from simulation to FPGA implementation", Journal of Telecommunications and Information Technology (JTIT), 2016


  • Büchner, S., Nolte, J., Kraemer, R., Lopacinski, L., and Karnapke, R. , "Challenges for 100 gbit/s End to End Communication: Increasing Throughput Through Parallel Processing.", In 40th Annual IEEE Conference on Local Computer Networks (LCN 2015), pages 607–610, Clearwater Beach/USA., 2015
  • Lopacinski L., Brzozowski M., and Kraemer R., "A 100 Gbps data link layer with a frame segmentation and hybrid automatic repeat request.", In Science and Information Conference 2015, London/United Kingdom , 2015
  • Lopacinski, L., Nolte, J., Buechner, S., Brzozowski, M., and Kraemer, R., "100 Gbps Wireless – Data Link Layer VHDL Implementation", In Proc. of the 18th Conference on Reconfigurable Ubiquitous Computing, Szczecin/Poland, 2015
  • Lopacinski, L., Nolte, J., Büchner, S., Brzozowski, M., and Kraemer, R., "Parallel RS error correction structures dedicated for 100 Gbps wireless data link layer.", In 15th IEEE International Conference on Ubiquitous Wireless Broadband 2015: Special Session on Wireless Terahertz Communications (IEEE ICUWB 2015 SPS 02), Montreal/Canada, 2015
  • Lopacinski, L., Nolte, J., Buechner, S., Brzozowski, M., and Kraemer, R., "Design and performance measurements of an fpga accelerator for a 100 Gbps wireless data link layer.", In IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS2015), 2015
  • Lopacinski, L., Nolte, J., Buechner, S., Brzozowski, M., and Kraemer, R., "A 100 Gbps data link layer with an adaptive algorithm for forward error correction", In Proc. IEICE Information and Communication Technology Forum (IEICE ICTF), Manchester/United Kingdom.
  • Lopacinski, L., Nolte, J., Buechner, S., Brzozowski, M., and Kraemer, R., "Design and Performance Measurements of an FPGA Accelerator for a 100 Gbps Wireless Data Link Layer", in Proc. International Symposium on Signals, Systems and Electronics (ISSSE), Gran Canaria, Spain., 2015


  • Lopacinski L., Brzozowski M., Kraemer R., Nolte J., “100 Gbps Wireless - Challenges to the Data Link Layer”, in Proc. IEICE Information and Communication Technology Forum, Poznan/Poland., 2014