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Fakultät 1
Fachgebiet Technische Informatik Vertretungsprofessur Dr.-Ing. habil. Christian Herglotz

akademischer Mitarbeiter

M.Sc. Keyvan Shahin

Verfügungsgebäude 1C, Raum 1.39

T: +49 (0) 355 69
F: +49 (0) 355 69 2027
keyvan.shahin(at)b-tu.de

Work and Education
  • (2020-now) Research Worker/Ph.D. Student, Brandenburg University of Technology, TECI chair, Cottbus, Germany
  • (2017-2020) Research Worker/Ph.D. Student, Ruhr University of Bochum, ESIT chair, Bochum, Germany
  • (2015-2017) Digital Hardware Designer for Embedded Systems, MECO (MAPNA), Karaj, Iran
  • (2013-2015) Digital Hardware Designer, Aria Wave, Tehran, Iran
  • (2013-2013) Digital System Engineer, SAMA, Tehran, Iran
  • ( 2009-2011 ) M.Sc. Digital Systems. Sharif University of Technology, Tehran, Iran
  • (2004-2009) B.Sc. Electrical Engineering-Electronics, Shahid Beheshti University, Tehran, Iran
Research Interests

Scientific Interests:

  • Hardware Developement on FPGAs and ASICs
  • Hardware/FPGA-Based Acceleration
  • Embedded Systems
  • Communication Hardware Implementation
  • Design Optimization and Design Spcae Exploration
  • DSP Systems Implementation

Available Topics for Students:

Autonomous Drone Swarm:

We are actively seeking individuals who are passionate about contributing to cutting-edge projects, particularly those intrigued by the exciting developments in our iCampus initiative, with a focus on a specialized package named UPWARDS.

Within UPWARDS, our primary objective is to establish a robust framework for orchestrating a swarm of drones to autonomously execute missions. This ambitious endeavor involves the development of a sophisticated middleware that plays a pivotal role in seamlessly transferring sensor data to decision-making units. Simultaneously, the middleware facilitates the transmission of crucial commands between the drones and the ground station.

By joining our team, you'll have the unique opportunity to be at the forefront of drone technology innovation, working on the intricacies of autonomy, data management, and communication systems. If you are enthusiastic about pushing the boundaries of what is possible in unmanned aerial systems, we invite you to explore the possibilities within the iCampus project and contribute to the groundbreaking work we are doing in the UPWARDS package. Your expertise and passion can make a significant impact on the future of autonomous drone missions.

Hardware/FPGA-Based acceleration of floating-point to fixed-point conversion

The realm of Digital Signal Processing (DSP) systems and algorithms relies on the nuanced use of fixed-point and floating-point numeric representations. While general-purpose computers and software-based tools predominantly employ floating-point representation to model and simulate arithmetic operations in DSP systems, the landscape shifts when it comes to implementing hardware solutions, such as Field-Programmable Gate Arrays (FPGAs) or Application-Specific Integrated Circuits (ASICs). In these scenarios, leveraging fixed-point representation often proves markedly more efficient in terms of both area utilization and processing speed.

Despite the prevalence of floating-point representation in software-based tools, the hardware implementation of DSP algorithms necessitates a crucial step: the conversion from floating-point to fixed-point representation. This transformation is pivotal for translating the algorithm's software description into a form conducive to hardware execution. It has been observed that the conversion process, a vital aspect of design, can consume up to 30% of the overall design time, depending on the complexity of the algorithm. Moreover, it can pose a challenging and labor-intensive task for designers.

To date, prevailing approaches for this conversion have been predominantly software-based. While there have been mentions of the potential use of FPGAs to execute this conversion, a comprehensive and methodical framework for a general hardware-based fixed-point simulation has, to the best of our knowledge, been lacking.

This work addresses this gap by introducing a novel FPGA-based hardware framework. This framework incorporates a width-configurable hardware architecture, designed to significantly reduce the execution time of the floating-point to fixed-point conversion process when compared to traditional software-based approaches. By optimizing this critical stage of the design process, our approach not only enhances efficiency but also lays the foundation for advancing the broader field of hardware-accelerated fixed-point simulations in DSP systems.

Publications

Check out my publications list in Google Scholar

A width-configurable hardware approach for accelerating fixed-point simulation

Autor(en)
Shahin, Keyvan, Hübner, Michael, Herglotz, Christian
Publikationsart
Konferenzveröffentlichung referiert
Erscheinungsjahr
2025
Verlag
Piscataway, NJ : IEEE
Freie Schlagworte
Fixed-Point Simulation, Width-Configurable Hardware, Hardware-based Acceleration, High-Level Synthesis (HLS)
Quelle
IEEE Computer Society Annual Symposium on VLSI (ISVLSI)
ISBN
979-8-3315-3477-6
DOI
https://doi.org/10.1109/ISVLSI65124.2025.11130205

Towards complete open-source environments : FPGA-based GPU overlay controlled by RISC-V

Autor(en)
Muñoz-Hernandez, Hector Gerardo, Ali, Muhammad, Shahin, Keyvan, Siyavashi, Alireza, Göhringer, Diana, Reichenbach, Marc, Herglotz, Christian, Hübner, Michael
Publikationsart
Konferenzveröffentlichung referiert
Erscheinungsjahr
2025
Verlag
Berlin : Springer
Freie Schlagworte
FPGA; Soft-core GPU; System-On-Chip; RISC-V; HBM
Quelle
Architecture of computing systems : 38th International Conference, ARCS 2025Kiel, Germany, April 22–24, 2025, proceedings, S. 94 - 108
ISBN
978-3-032-03280-5
DOI
https://doi.org/https://doi.org/10.1007/978-3-032-03281-2_7
Schriftenreihe(n) ; Bandnummer
Lecture Notes in Computer Science ; 15839

Designing intelligent sensor networks : a comprehensive survey of sensing, edge AI, and 5G+/6G connectivity

Autor(en)
Herglotz, Christian, Jabłoński, Ireneusz, Karnapke, Reinhardt, Shahin, Keyvan, Reichenbach, Marc
Publikationsart
Wissenschaftlicher Zeitschriftenartikel referiert
Erscheinungsjahr
2025
Verlag
Piscataway, NJ : IEEE
Freie Schlagworte
5G, Sensor networks, Edge computing, Energy efficiency, KPIs, Design space, AI
Quelle
IEEE access, S. 172306 - 172325
Band/Jahrgang
13
ISSN
2169-3536
DOI
https://doi.org/10.1109/ACCESS.2025.3615205

A Modular Communication Architecture for Adaptive UAV Swarms

Autor(en)
Shahin, Keyvan, Rotta, Randolf, Archila, Oscar, Mykytyn, Pavlo, Nattke, Matthias, Reichenbach, Marc, Nolte, Jörg, Natarov, Roman
Publikationsart
Konferenzveröffentlichung referiert
Erscheinungsjahr
2023
Verlag
Berlin : IEEE
Quelle
2023 IEEE International Conference on Omni-layer Intelligent Systems (COINS)
ISBN
979-8-3503-4647-3
979-8-3503-4648-0
DOI
https://doi.org/10.1109/COINS57856.2023.10189245

Accelerating fixed-point simulations using width reconfigurable hardware architectures

Autor(en)
Shahin, Keyvan, Hübner, Michael
Publikationsart
Konferenzveröffentlichung referiert
Erscheinungsjahr
2021
Verlag
Piscataway, NJ : IEEE
Freie Schlagworte
Computers, Computational modeling, Signal processing algorithms, Digital signal processing, Tools, Hardware, Numerical models
Quelle
31st International Conference on Field-Programmable Logic and Applications (FPL), Dresden, Germany, 30 August-3 September 2021, S. 275 - 276
ISBN
978-1-6654-3759-2
DOI
https://doi.org/10.1109/FPL53798.2021.00055

Domain Adaptive Processor Architectures

Autor(en)
Fricke, Florian, Mahmood, Safdar, Hoffmann, Javier Eduardo, Ali, Muhammad, Shahin, Keyvan, Hübner, Michael, Göhringer, Diana
Publikationsart
Konferenzveröffentlichung referiert
Erscheinungsjahr
2020
Quelle
Kommunikation und Bildverarbeitung in der Automation, S. 315 - 330
ISBN
978-3-662-59895-5
978-3-662-59894-8
DOI
https://doi.org/10.1007/978-3-662-59895-5_23
Schriftenreihe(n) ; Bandnummer
Technologien für die intelligente Automation book series ; volume 12

Automatic Toolflow for VCGRA Generation to Enable CGRA Evaluation for Arithmetic Algorithms

Autor(en)
Werner, André, Fricke, Florian, Shahin, Keyvan, Werner, Florian, Hübner, Michael
Herausgeber
Hochberger, Christian, Nelson, Brent, Koch, Andreas, Woods, Roger, Diniz, Pedro C.
Publikationsart
Wissenschaftlicher Zeitschriftenartikel nicht referiert
Erscheinungsjahr
2019
Verlag
Cham : Springer
Quelle
Applied Reconfigurable Computing, 15th International Symposium, ARC 2019, Darmstadt, Germany, April 9–11, 2019, Proceedings, S. 277 - 291
ISSN
0302-9743
1611-3349
ISBN
978-3-030-17226-8
978-3-030-17227-5
DOI
https://doi.org/0.1007/978-3-030-17227-5_20
Schriftenreihe(n) ; Bandnummer
Lecture Notes in Computer Science book series ; volume 11444
Theoretical Computer Science and General Issues book sub series ; volume 11444

Automatic Tool-Flow for Mapping Applications to an Application-Specific CGRA Architecture

Autor(en)
Fricke, Florian, Werner, André, Shahin, Keyvan, Werner, Florian, Hübner, Michael
Publikationsart
Konferenzveröffentlichung referiert
Erscheinungsjahr
2019
Quelle
IEEE International Symposium on Parallel and Distributed Processing, Workshops and Phd Forum (IPDPSW), S. 147 - 154
ISBN
978-1-7281-3510-6
978-1-7281-3511-3
DOI
https://doi.org/10.1109/IPDPSW.2019.00033

CGRA Tool Flow for Fast Run-Time Reconfiguration

Autor(en)
Fricke, Florian, Werner, André, Shahin, Keyvan, Hübner, Michael
Herausgeber
Voros, Nikolaos, Hübner, Michael, Keramidas, Georgios, Göhringer, Diana, Antonopoulos, Christos, Diniz, Pedro C.
Publikationsart
Konferenzveröffentlichung
Erscheinungsjahr
2018
Verlag
Cham : Springer
Quelle
Proceedings, 14th International Symposium on Applied Reconfigurable Computing, Santorini, Greece, May 2-4, 2018, S. 661 - 672
ISBN
978-3-319-78889-0
978-3-319-78890-6
DOI
https://doi.org/10.1007/978-3-319-78890-6_53